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| PRESETTABLE BCD/DECADE UP/DOWN COUNTERS PRESETTABLE 4-BIT BINARY UP/DOWN COUNTERS The SN54 / 74LS190 is a synchronous UP/ DOWN BCD Decade (8421) Counter and the SN54/ 74LS191 is a synchronous UP / DOWN Modulo-16 Binary Counter. State changes of the counters are synchronous with the LOW-to-HIGH transition of the Clock Pulse input. An asynchronous Parallel Load (PL) input overrides counting and loads the data present on the Pn inputs into the flip-flops, which makes it possible to use the circuits as programmable counters. A Count Enable (CE) input serves as the carry / borrow input in multi-stage counters. An Up / Down Count Control (U/D) input determines whether a circuit counts up or down. A Terminal Count (TC) output and a Ripple Clock (RC) output provide overflow/underflow indication and make possible a variety of methods for generating carry / borrow signals in multistage counter applications. SN54/74LS190 SN54/74LS191 PRESETTABLE BCD/ DECADE UP/ DOWN COUNTERS PRESETTABLE 4-BIT BINARY UP/ DOWN COUNTERS LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 620-09 16 1 * * * * * * * * Low Power . . . 90 mW Typical Dissipation High Speed . . . 25 MHz Typical Count Frequency Synchronous Counting Asynchronous Parallel Load Individual Preset Inputs Count Enable and Up/ Down Control Inputs Cascadable Input Clamp Diodes Limit High Speed Termination Effects CONNECTION DIAGRAM DIP (TOP VIEW) V CC 16 P 0 15 CP 14 RC 13 TC 12 PL 11 P 2 10 P 3 9 16 1 N SUFFIX PLASTIC CASE 648-08 16 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC 1 P 1 2 Q 1 3 Q 0 4 CE 5 U/D 6 Q 2 7 Q 3 8 GND LOGIC SYMBOL 11 15 1 10 9 PIN NAMES LOADING (Note a) HIGH LOW 0.7 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 (2.5) U.L. 5 (2.5) U.L. 5 (2.5) U.L. PL 5 U/D P 0 P P 1 2 P 3 RC 13 CE CP U/D PL Pn Qn RC TC Count Enable (Active LOW) Input Clock Pulse (Active HIGH going edge) Input Up/Down Count Control Input Parallel Load Control (Active LOW) Input Parallel Data Inputs Flip-Flop Outputs (Note b) Ripple Clock Output (Note b) Terminal Count Output (Note b) 1.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. 10 U.L. 10 U.L. 4 14 CE CP Q 0 Q 1 Q 2 Q 3 TC 12 3 2 6 7 V = PIN 16 CC GND = PIN 8 NOTES: a. 1 TTL Unit Load (U.L.) = 40 A HIGH/1.6 mA LOW. b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) b. Temperature Ranges. FAST AND LS TTL DATA 5-341 SN54/74LS190 * SN54/74LS191 STATE DIAGRAMS 0 1 2 3 4 0 1 2 3 4 LS190 UP: 15 5 DOWN: TC = Q0 TC = Q0 Q3 (U/D) Q1 Q2 Q3 (U/D) 15 5 14 6 UP: DOWN: LS191 TC = Q0 Q1 Q2 Q3 (U/D) TC = Q0 Q1 Q2 Q3 (U/D) 14 6 13 7 COUNT UP 13 7 12 11 10 9 8 COUNT DOWN 12 11 10 9 8 LS190 LS191 LOGIC DIAGRAMS CP 14 U/D 5 P0 15 CE 4 P1 1 P2 10 P3 9 PL 11 J CLOCK K J CLOCK K J CLOCK K J CLOCK K PRESET Q CLEAR Q PRESET Q CLEAR Q PRESET Q CLEAR Q PRESET Q CLEAR Q 13 12 3 2 6 7 RC TC Q0 Q1 Q2 Q3 VCC = PIN 16 GND = PIN 8 = PIN NUMBERS DECADE COUNTER LS190 FAST AND LS TTL DATA 5-342 SN54/74LS190 * SN54/74LS191 LOGIC DIAGRAMS (continued) CP 14 U/D 5 P 0 15 CE 4 P 1 1 P 2 10 P 3 9 PL 11 J CLOCK K J CLOCK K J CLOCK K J CLOCK K PRESET Q CLEAR Q PRESET Q CLEAR Q PRESET Q CLEAR Q PRESET Q CLEAR Q 13 12 3 2 6 7 RC TC Q 0 Q 1 Q 2 Q 3 V = PIN 16 CC GND = PIN 8 = PIN NUMBERS BINARY COUNTER LS191 FAST AND LS TTL DATA 5-343 SN54/74LS190 * SN54/74LS191 FUNCTIONAL DESCRIPTION The LS190 is a synchronous Up / Down BCD Decade Counter and the LS191 is a synchronous Up / Down 4-Bit Binary Counter. The operating modes of the LS190 decade counter and the LS191 binary counter are identical, with the only difference being the count sequences as noted in the state diagrams. Each circuit contains four master / slave flip-flops, with internal gating and steering logic to provide individual preset, count-up and count-down operations. Each circuit has an asynchronous parallel load capability permitting the counter to be preset to any desired number. When the Parallel Load (PL) input is LOW, information present on the Parallel Data inputs (P0 - P3) is loaded into the counter and appears on the Q outputs. This operation overrides the counting functions, as indicated in the Mode Select Table. A HIGH signal on the CE input inhibits counting. When CE is LOW, internal state change are initiated synchronously by the LOW-to-HIGH transition of the clock input. The direction of counting is determined by the U/D input signal, as indicated in the Mode Select Table. When counting is to be enabled, the CE signal can be made LOW when the clock is in either state. However, when counting is to be inhibited, the LOW-to-HIGH CE transition must occur only while the clock is HIGH. Similarly, the U / D signal should only be changed when either CE or the clock is HIGH. Two types of outputs are provided as overflow/underflow indicators. The Terminal Count (TC) output is normally LOW and goes HIGH when a circuit reaches zero in the count-down mode or reaches maximum (9 for the LS190, 15 for the LS191) in the count-up mode. The TC output will then remain HIGH until a state change occurs, whether by counting or presetting or until U / D is changed. The TC output should not be used as a clock signal because it is subject to decoding spikes. The TC signal is also used internally to enable the Ripple Clock (RC) output. The RC output is normally HIGH. When CE is LOW and TC is HIGH, the RC output will go LOW when the clock next goes LOW and will stay LOW until the clock goes HIGH again. This feature simplifies the design of multi-stage counters, as indicated in Figures a and b. In Figure a, each RC output is used as the clock input for the next higher stage. This configuration is particularly advantageous when the clock source has a limited drive capability, since it drives only the first stage. To prevent counting in all stages it is only necessary to inhibit the first stage, since a HIGH signal on CE inhibits the RC output pulse, as indicated in the RC Truth Table. A disadvantage of this configuration, in some applications, is the timing skew between state changes in the first and last stages. This represents the cumulative delay of the clock as it ripples through the preceding stages. A method of causing state changes to occur simultaneously in all stages is shown in Figure b. All clock inputs are driven in parallel and the RC outputs propagate the carry / borrow signals in ripple fashion. In this configuration the LOW state duration of the clock must be long enough to allow the negative-going edge of the carry / borrow signal to ripple through to the last stop before the clock goes HIGH. There is no such restriction on the HIGH state duration of the clock, since the RC output of any package goes HIGH shortly after its CP input goes HIGH. The configuration shown in Figure c avoids ripple delays and their associated restrictions. The CE input signal for a given stage is formed by combining the TC signals from all the preceding stages. Note that in order to inhibit counting an enable signal must be included in each carry gate. The simple inhibit scheme of Figures a and b doesn't apply, because the TC output of a given stage is not affected by its own CE. MODE SELECT TABLE INPUTS MODE PL H H L H CE L L X H U/D L H X X CP Count Up Count Down Preset (Asyn.) No Change (Hold) CE L H X RC TRUTH TABLE INPUTS TC* H X L CP X X RC OUTPUT X X H H * TC is generated internally L = LOW Voltage Level H = HIGH Voltage Level X = Don't Care = LOW-to-HIGH Clock Transition = LOW Pulse FAST AND LS TTL DATA 5-344 SN54/74LS190 * SN54/74LS191 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current -- High Output Current -- Low Parameter 54 74 54 74 54, 74 54 74 Min 4.5 4.75 - 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 - 0.4 4.0 8.0 Unit V C mA mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54, 74 VOL Output LOW Voltage 74 Input HIGH Current Other Inputs CE Other Inputs CE IIL IOS ICC Input LOW Current Other Inputs CE Short Circuit Current (Note 1) Power Supply Current - 20 0.35 0.5 20 60 0.1 0.3 - 0.4 - 1.2 - 100 35 V A 2.7 3.5 0.25 0.4 V V 2.5 - 0.65 3.5 0.8 - 1.5 V V Min 2.0 0.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN, IIN = - 18 mA VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table IOL = 4.0 mA IOL = 8.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table VCC = MAX, VIN = 2.7 V IIH mA VCC = MAX, VIN = 7.0 V mA mA mA VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. FAST AND LS TTL DATA 5-345 SN54/74LS190 * SN54/74LS191 AC CHARACTERISTICS (TA = 25C) Limits Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Parameter Maximum Clock Frequency Propagation Delay, PL to Output Q Data to Output Q Clock to RC Clock to Output Q Clock to TC U / D to RC U / D to TC CE to RC Min 20 Typ 25 22 33 20 27 13 16 16 24 28 37 30 30 21 22 21 22 33 50 32 40 20 24 24 36 42 52 45 45 33 33 33 33 Max Unit MHz ns ns ns ns ns ns ns ns VCC = 5.0 V CL = 15 pF Test Conditions AC SETUP REQUIREMENTS (TA = 25C) Limits Symbol tW tW ts th trec Parameter CP Pulse Width PL Pulse Width Data Setup Time Data Hold Time Recovery Time Min 25 35 20 5.0 40 Typ Max Unit ns ns ns ns ns VCC = 5.0 V Test Conditions DEFINITIONS OF TERMS SETUP TIME (ts) is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW-to-HIGH in order to be recognized and transferred to the outputs. HOLD TIME (th) is defined as the minimum time following the clock transition from LOW-to-HIGH that the logic level must be maintained at the input in order to ensure continued recognition. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOWto-HIGH and still be recognized. RECOVERY TIME (trec) is defined as the minimum time required between the end of the reset pulse and the clock transition from LOW-to-HIGH in order to recognize and transfer HIGH data to the Q outputs. FAST AND LS TTL DATA 5-346 SN54/74LS190 * SN54/74LS191 DIRECTION CONTROL U/D ENABLE CLOCK CE CP RC U/D CE CP RC U/D CE CP RC Figure a. n-Stage Counter Using Ripple Clock DIRECTION CONTROL U/D ENABLE CE CP RC U/D CE CP RC U/D CE CP RC CLOCK Figure b. Synchronous n-Stage Counter Using Ripple Carry / Borrow DIRECTION CONTROL ENABLE U/D CE CP TC U/D CE CP TC U/D CE CP TC CLOCK Figure c. Synchronous n-Stage Counter with Parallel Gated Carry / Borrow FAST AND LS TTL DATA 5-347 SN54/74LS190 * SN54/74LS191 AC WAVEFORMS 1/f MAX tW CP 1.3 V 1.3 V CP OR CE 1.3 V 1.3 V tPHL Q OR TC 1.3 V tPLH 1.3 V RC tPHL 1.3 V tPLH 1.3 V Figure 1 Figure 2 Pn tPHL 1.3 V 1.3 V tPLH Pn tW Qn 1.3 V PL 1.3 V tPLH 1.3 V tPHL NOTE: PL = LOW Qn Figure 3 Figure 4 Pn PL tW 1.3 V 1.3 V ts(H) PL 1.3 V th(H) 1.3 V th(L) ts(L) 1.3 V 1.3 V trec CP Qn Q Q=P Q=P * The shaded areas indicate when the input is permitted * to change for predictable output performance Figure 5 Figure 6 U/D 1.3 V th(L) th(H) tPLH 1.3 V tPHL 1.3 V CP 1.3 V ts(L) 1.3 V ts(H) TC tPHL tPLH CE CE MAY CHANGE (H L) only CE MAY CHANGE 1.3 V RC 1.3 V 1.3 V Figure 7 Figure 8 FAST AND LS TTL DATA 5-348 -A- Case 751B-03 D Suffix 16-Pin Plastic SO-16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. 3. CONTROLLING DIMENSION: MILLIMETER. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. 751B 01 IS OBSOLETE, NEW STANDARD 751B 03. 16 9 -B1 8 P 8 PL 0.25 (0.010) M B M R X 45 G -TD 16 PL 0.25 (0.010) M C SEATING PLANE K T B S M F J A S DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 3.80 1.35 0.35 0.40 10.00 4.00 1.75 0.49 1.25 INCHES MIN MAX 0.386 0.150 0.054 0.014 0.016 0.393 0.157 0.068 0.019 0.049 1.27 BSC 0.19 0.10 0 5.80 0.25 0.25 0.25 7 6.20 0.50 0.050 BSC 0.008 0.004 0 0.229 0.010 0.009 0.009 7 0.244 0.019 Case 648-08 N Suffix 16-Pin Plastic -A16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. 3. CONTROLLING DIMENSION: INCH. DIMENSION L" TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B" DOES NOT INCLUDE MOLD FLASH. 5. 6. ROUNDED CORNERS OPTIONAL. 648 01 THRU 07 OBSOLETE, NEW STANDARD 648 08. B 1 8 F S C -TK SEATING PLANE L H G D 16 PL 0.25 (0.010) M J M T A M DIM A B C D F G H J K L M S MILLIMETERS MIN MAX 18.80 6.35 3.69 0.39 1.02 19.55 6.85 4.44 0.53 1.77 INCHES MIN MAX 0.740 0.250 0.145 0.015 0.040 0.770 0.270 0.175 0.021 0.070 2.54 BSC 1.27 BSC 0.21 2.80 7.50 0 0.51 0.38 3.30 7.74 10 1.01 0.100 BSC 0.050 BSC 0.008 0.110 0.295 0 0.020 0.015 0.130 0.305 10 0.040 -A16 9 Case 620-09 J Suffix 16-Pin Ceramic Dual In-Line NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. -B1 8 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIM F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. C L 5. 620 01 THRU 08 OBSOLETE, NEW STANDARD 620 09. -TSEATING PLANE K E F D 16 PL 0.25 (0.010) M N G T A S M J 16 PL 0.25 (0.010) M T B S DIM A B C D E F G J K L M N MILLIMETERS MIN MAX 19.05 6.10 19.55 7.36 4.19 0.39 0.53 INCHES MIN MAX 0.750 0.240 0.770 0.290 0.165 0.015 0.021 1.27 BSC 1.40 1.77 0.050 BSC 0.055 0.070 2.54 BSC 0.23 0.27 5.08 7.62 BSC 0 0.39 15 0.88 0.100 BSC 0.009 0.011 0.200 0.300 BSC 0 0.015 15 0.035 FAST AND LS TTL DATA 5-349 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Literature Distribution Centers: USA: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. EUROPE: Motorola Ltd.; European Literature Centre; 88 Tanners Drive, Blakelands, Milton Keynes, MK14 5BP, England. JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan. ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. FAST AND LS TTL DATA 5-350 |
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